K1921VG7U

K1921VG7U
A 32-bit, low-pin RISC-V microcontroller designed for building IoT systems. Contains 256 KB of non-volatile memory, a set of universal and specialized blocks and interfaces.

The product will be available for purchase in the first quarter of 2026.

Description

Application area: The MCU can be applied in measuring, communication, surveillance, security systems, in industrial automation, medicine, energy and industry devices including electric drives, as well as in various control systems.

Composition and features:

- a general-purpose 32-bit RISC-V processor core based on architecture of Russian design (32-bit, 32 registers, with built-in multiplier, floating point unit, debugger)
–  8-channel general purpose DMA controller;
– 64 KByte SRAM data memory
– 2556 Kbyte Flash program memory and interrupt call upon completion of recording/clearing operations;
–  watchdog timer (WatchDog);
–battery-powered real-time clock RTC clocked from an external 32.768 kHz generator, with generation control and automatic transition to the internal generator in case of failures,supporting following modes:

  • connectionwith an external resonator (or generator) 32.768 kHz,
  • SLEEP mode operation;

–two 32-bit multi-function timers with PWM support with the following features:

  • individual period registers,
  • the ability to clock the timer from the controller pin,
  • separate divider for each timer,
  • the ability to start a timer on the overflow event of another timer,
  • selectable counting direction (up/down),
  • timer overflow event interruption;

–three 16-bit multi-function timers with PWM support and following features:

  • individual period registers,
  • the ability to clock the timer from the controller pin,
  • separate divider for each timer,
  • the ability to start a timer on the overflow event of another timer,
  • selectable counting direction (up/down),
  • timer overflow event interruption;

–five PWM generation channels based on multifunctional timers with the following features:

  • independent signal period registers,
  • unable to delay the output signal generation by a configurable number of clock cycles ,
  • the ability to divide the module's input clock frequency by at least 256
  • each capture/comparison unit is connected to a separate peripheral and can be configured to an external event,
  • interrupt call on PWM signal period event,
  • for each capture/comparison unit, a same period values can be set in registers to use single capture block from timers;

– CAN interface port;
– two UART ports;
– two SPI ports with the following features:

  • SSI, Motorola, Microwire protocols,
  • polarity and phase adjustment,
  • at least 2 alternative output options for each block,
  • software control of the exchange rate,
  • programmable 4-to-16-bit information frame duration ,
  • frequency of up to 40 MHz in master mode and up to 6.67 MHz in slave mode;

– control interface for an external radio frequency transceiver based on the SPI interface (RF interface Tx/Rx);
– I2C two I2C interface controllers;
– eight-channel 12-bit ADC with the following features:

  • 1 MSPS maximum conversion speed
  • operation under control of two sequencers, each allowing to independently launch measurements on the required ADC channels and generate an interrupt,conversion start on the external clock signal (timer, port, PWM),
  • single and cyclic restart operating modes, with the possibility to average results
  • 8 independent digital comparators that track and compare measurement results with threshold values to generate interrupts and control signals for other microcontroller blocks
  • twelve measurement result buffers (each organized as FIFO),
  • 2 levels of channel priority;

– temperature sensor;
–General Purpose Input Output (GPIO) ports with the following features:

  • 16-bit capacity,
  • custom settings for each pin,
  • possibility to change the state of the output pin by an additional register (SET, CLEAR, TOGGLE, masked output),
  • possibility to set interruptions based on configurable edges of the input signal;

– QFN-48 package.